1. Field of the Invention
The invention relates to a driver circuit for an AC plasma display panel, and more particularly to an energy recovery sustain circuit for driving an AC plasma display panel.
2. Description of the Related Art
It has been required for improvement in the low power consumption to develop a low power driver circuit for driving the AC plasma display device. It has been proposed in the prior arts to use the driver circuit for driving the AC plasma display panel, which includes an inductor to recover the majority of the energy which is normally lost in charging and discharging operations of the panel capacitance and thus the load capacitance. Such an energy recovery function of the inductor is accomplished by a series connection of the inductor and the load capacitor. The conventional energy recovery circuits for driving the AC plasma display circuit is disclosed in SID 87 Digest, pp. 92-95, "Energy Recovery Circuit for the AC Plasma Display".
A typical one of the conventional energy recovery circuit for driving the AC plasma display circuit will be described with reference to FIG. 1. The energy recovery circuit has an inductor L1 which is connected in series to a load capacitor C.sub.L through an output terminal OUT for forming the LC resonance circuit to recover most of the energy which is normally lost in charging and discharging the load capacitor. The load capacitor C.sub.L physically comprises a parasitic capacitance such as line-to-line parasitic capacitance. When the driver circuit driven with a frequency f.sub.0 has no inductor, a power of f.sub.0.sup.. C.sub.L.sup.. V.sub.0.sup.2 is consumed in charging and discharging operations of the load capacitance C.sub.L. The output terminal is connected to a high voltage line applied with a voltage V.sub.0 through a p-channel MOS transistor MP2 which serves to sustain a V.sub.0 output voltage appearing at the output terminal. The output terminal is connected to a ground line taking the ground potential through an n-channel MOS transistor MN2 which serves to sustain the zero output voltage appearing at the output terminal. The inductor L1 is connected at its input side to both an output side of a diode D1 and an input side of a diode D2, both of which are connected to each other. The diode D1 is connected through a p-channel MOS transistor MP1 to a capacitor C1 which has a sufficiently larger capacitance than that of the load capacitor C.sub.L. The transistor MP1 serves as a switch for discharging the capacitor C1 and subsequently charging the load capacitor C.sub.L. The diode D2 is connected to the capacitor C1 through an n-channel MOS transistor MN1 serving as a switch for discharging the load capacitor C.sub.L and subsequently charging the capacitor C1.
The charging and discharging operations of the conventional energy recovery circuit will be described with reference to FIG. 2 illustrative of wave-forms of the output voltage and the output current at the output terminal and a voltage at the input side N1 of the inductor L1 as well as respective gate voltages of the transistors MP1, MP2, MN1 and MN2. The charging operation and subsequent discharging operation of the load capacitor C.sub.L may be divided into four time durations and thus T1, T2, T3 and T4.
In the time duration T1, the output voltage appearing at the output terminal OUT is raised for conducting the charging operation of the load capacitor C.sub.L. The transistor MP1 is applied with a low level signal and then turns ON. The transistor MP2 is applied with a high level signal and then remains in the OFF state. The transistors MN1 and MN2 are applied with a low level signal and then assume the OFF state. Namely, in the time duration T1, only the transistor MP1 takes the ON state and the others take the OFF state and thereby an equivalent LC circuit as illustrated in FIG. 3 is formed. The capacitor C1 then shows the discharge and the discharge current flows through the transistor MP1 and the diode D1. Further, the discharge current flows through the inductor L1 and then appears at the output terminal OUT, resulting in the charge-up operation of the load capacitor C.sub.L which will be completed after the time duration T1. The load capacitor is charged up to the voltage level V.sub.0.
The high voltage sustain operation of the load capacitor C.sub.L in the second time duration T2 follows the charging operation of the load capacitor C.sub.L in the first time duration T1. The output voltage V.sub.0 appearing at the output terminal OUT is sustained for the second time duration. The transistor MP1 is still applied with a low level signal and then remains in the ON state. The transistor MP2 is applied with a low level signal and then turns ON. The transistor MN1 and MN2 are still applied with a low level signal and then remain in the OFF state. Namely, in the time duration T2, the transistors MP1 and MP2 take the ON state and the others take the OFF state. The voltage V.sub.0 is supplied from the high voltage line through the transistor MP2 to the output terminal OUT thereby the output voltage V.sub.0 applied to the load capacitor C.sub.L is sustained for the second time duration T2.
In the third time duration, the discharging operation of the load capacitance C.sub.L is performed. The output voltage V.sub.0 appearing at the output terminal OUT drops for the third time duration. The transistors MP1 and MP2 are applied with a high level signal and then turn OFF. The transistor MN1 is applied with a high level signal and then turns ON. The transistor MN2 is still applied with a low level signal and then remains in the OFF state. Namely, in the time duration T3, only the transistor MN1 takes the ON state and the others take the OFF state. The load capacitor C.sub.L then shows the discharge and the discharge current from the load capacitor C.sub.L appears and then flows through the inductor L1, the diode D2 and the transistor MN1 into the capacitor C1, resulting in a charge up operation of the capacitor C1. The load capacitor C.sub.L discharges until the output voltage drops to zero voltage.
The zero voltage sustain operation of the output voltage in the fourth time duration T4 follows the discharging operation of the load capacitor C.sub.L in the third time duration T3. The zero output voltage appearing at the output terminal OUT is sustained for the fourth time duration. The transistor MP1 is still applied with a low level signal and then remains in the ON state. The transistors MP1 and MP2 are applied with a high level signal and then remain in the OFF state. The transistor MN1 is still applied with a high level signal and then remains in the ON state. The transistor MN2 is applied with a high level signal and then turns ON. Namely, in the time duration T4, the transistors MN1 and MN2 take the ON state and the others take the OFF state. The ground potential or the zero voltage is supplied from the ground line through the transistor MN2 to the output terminal OUT thereby the zero output voltage applied to the load capacitor C.sub.L is sustained.
As described above, since the charging and discharging currents flow through the inductor C.sub.L, the LC resonance circuit operation appears, and thereby the energy recovery effect is obtained. Namely, an energy lost in discharging the capacitor C1 is used to charge up the load capacitor C.sub.L. The energy which has been used to charge up the load capacitor C.sub.L is subsequently discharged from the load capacitor C.sub.L and then used to charge up the capacitor C1. That is how the energy recovery is accomplished.
It is of course impossible to recover the exact energy because the transistors MP1 and MN1 serving as the switches as well as the diodes D1 and D2 both have internal resistances through which the charge or the discharge currents flow. It is general that the p-channel MOS transistor has a large ON-resistance as compared to that of the n-channel MOS transistor. The improvement in the efficiency of the energy recovery requires a reduction of the ON-resistance thereof. But the reduction of the resistance of the p-channel MOS requires an enlargement of the pellet size or the chip size which causes the parasitic capacitance between the source and drain to be enlarged. It is difficult to recover an energy lost due to parasitic capacitance in the energy recovery circuit in charging and discharging operations, resulting in a decrease in the efficiency of the energy recovery. That is why the improvement in the efficiency of the energy recovery is physically restricted.
In the current-voltage characteristic, the diodes D1 and D2 are forced to have specific forward bias rise voltages V.sub.F at which the forward current appears and it is increased rapidly in the voltage range more than the V.sub.F. The existence of the forward bias rise voltage V.sub.F in the diode causes the energy loss in the charging and discharging operations. Such the energy loss makes the efficiency of the energy recovery inferior. Particularly, such the problem in the inferiority of the efficiency of the energy recovery is considerable when the switching operation takes place at a voltage greater than 100 V because under the above condition a Schottky barrier diode having a relatively small forward bias rise voltage V.sub.F is not usable.
Further, in the prior art, each of the load capacitors and thus the plural pixel capacitors requires the energy recovery circuit when various pulse signals are applied to the pixel electrodes. The conventional driver circuit for the AC plasma display panel is thus expensive.
To settle the above problems, it is required to develop a novel driver circuit for a AC plasma display device.